`timescale 1ns / 10ps
`define clock_period 20

module voter_7bit_tb;

	reg[6:0] vote;
	wire pass;

	voter_7bit vote0(
		.Vote(vote),
		.Pass(pass)
	);
	
	initial begin
		
		vote = 7'b000_0000;
		#(`clock_period)
		vote = 7'b000_0001;
		#(`clock_period)
		vote = 7'b000_0011;
		#(`clock_period)
		vote = 7'b000_0111;
		#(`clock_period)
		vote = 7'b000_1111;
		#(`clock_period)
		vote = 7'b001_1111;
		#(`clock_period)
		vote = 7'b011_1111;
		#(`clock_period)
		vote = 7'b111_1111;
		#(`clock_period)
		
		$stop;
		
	end

endmodule
